//-----------------------------------------------------------------------------
//   File:      bulkloop.c
//   Contents:  Hooks required to implement USB peripheral function.
//
// $Archive: /USB/Examples/FX2LP/bulkloop/bulkloop.c $
// $Date: 3/23/05 2:55p $
// $Revision: 4 $
//
//
//-----------------------------------------------------------------------------
// Copyright 2003, Cypress Semiconductor Corporation
//-----------------------------------------------------------------------------
#pragma NOIV               // Do not generate interrupt vectors

#include "fx2.h"
#include "fx2regs.h"
#include "syncdly.h"            // SYNCDELAY macro

extern BOOL GotSUD;             // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;

BYTE Configuration;             // Current configuration
BYTE AlternateSetting;          // Alternate settings

typedef unsigned char u8;
typedef signed char s8;
typedef unsigned short u16;
typedef signed short s16;
typedef unsigned long u32;
typedef signed long s32;

void timer_init();
extern u16 us10_wait;

u8 val_ifconfig;
extern u16 ir_code;
extern u8 xdata ir_rbuf[256];
extern u8 xdata ir_wbuf[256];
extern u8 ir_wbuf_len, ir_wbuf_idx;
extern u8 ir_rbuf_idx;
u8 ir_rbuf_idx_cpy;

#define VR_NAKALL_ON    0xD0
#define VR_NAKALL_OFF   0xD1

void tty_out(s8 *s){
	u8 i=0;
	while(s[i]){
		if(s[i]=='\n'){
			SBUF0=0x0d;
			for(;;) if(TI==1) break;
			TI=0;
			SBUF0=0x0a;
		}
		else{
			SBUF0=s[i];
		}
		i++;
		for(;;){
			if(TI==1) break;
		}
		TI=0;
	}
}

const s8 hexchar[16]={
'0','1','2','3','4','5','6','7',
'8','9','A','B','C','D','E','F'
};

void tty_hex(u8 u){
	u8 s[3];
	s[0]=hexchar[u>>4];
	s[1]=hexchar[u & 0x0f];
	s[2]=0;
	tty_out(s);
}


//-----------------------------------------------------------------------------
// Task Dispatcher hooks
//   The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
u16 ret_cnt;

u8 int_flg;
u8 start_ts;
u8 start_tsbcas;
u8 poll_cnt;
u8 before_ep4bc;
u32 time_out;
u32 bcas_time_out;



void TD_Init(void)             // Called once at startup
{
	start_ts = 0;
	start_tsbcas = 0;
	before_ep4bc = 0xff;
	time_out = 0;
	int_flg = 0;
	poll_cnt=0;
	bcas_time_out = 0;


   // set the CPU clock to 48MHz and drive CLKOUT
   CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1 | bmCLKOE) ;

	//set FD bus 8bit
	EP2FIFOCFG = 0x04;
	SYNCDELAY;
	EP4FIFOCFG = 0x04;
	SYNCDELAY;
	EP6FIFOCFG = 0x04;
	SYNCDELAY;
	EP8FIFOCFG = 0x04;
	SYNCDELAY;

	//serial port init
	UART230=0x01;	//port0 set 115K baud
	SCON0    = 0x50; // 0101 0000 mode=1, REN_1=1
	TI       = 0;

//	tty_out("\n*** FX2 SPD_CHK by OPTIMIZE Ver1.00 ***");
//	tty_hex(0);
	
	timer_init();

	EP1OUTCFG = 0xA0;
	EP1INCFG = 0xA0;
	SYNCDELAY;                    // see TRM section 15.14
	EP1OUTBC = 0;

	REVCTL = 0x03; SYNCDELAY;		// see TRM 15.5.9

	EP2CFG = 0xA2;	//(OUT, Size = 512, buf = Quad (Buf x2), BULK);
	SYNCDELAY;                    

	EP4CFG = 0xE2;	//(IN, Size = 512, buf = Quad (Buf x2), BULK)
	SYNCDELAY;                    

	EP6CFG = 0xE0;	//(IN, Size = 512, buf = Quad (Buf x4), BULK) 
	SYNCDELAY;

	EP8CFG = 0x00;
	SYNCDELAY;                    

	FIFOPINPOLAR = 0x00; SYNCDELAY;
	EP4AUTOINLENH = 0x00; SYNCDELAY;
	EP4AUTOINLENL = 0x45; SYNCDELAY;
	EP6AUTOINLENH = 0x02; SYNCDELAY;
	EP6AUTOINLENL = 0x00; SYNCDELAY;

	FIFORESET = 0x80; SYNCDELAY; // activate NAK-ALL to avoid race conditions
	FIFORESET = 0x02; SYNCDELAY; // reset, FIFO 2
	FIFORESET = 0x04; SYNCDELAY; // reset, FIFO 4
	FIFORESET = 0x06; SYNCDELAY; // reset, FIFO 6
	FIFORESET = 0x08; SYNCDELAY; // reset, FIFO 8
	FIFORESET = 0x00; SYNCDELAY; // deactivate NAK-ALL

	// enable dual autopointer feature & inc
	AUTOPTRSETUP = 0x07;

	IOD = 0x00;	//MODE_IDLE
	OED = 0xc0;	//MODE is output

	PINFLAGSAB = 0xe8;	//FLAGA=ep2EF FLAGB=ep6FF
	SYNCDELAY;                    
}

#define	MODE_IDLE	(0<<6)
#define	MODE_REGR	(1<<6)
#define	MODE_REGW	(2<<6)
#define	MODE_START	(3<<6)

#define CMD_EP6IN_START		0x50	//
#define	CMD_EP6IN_STOP		0x51	//
#define	CMD_EP2OUT_START	0x52	//
#define	CMD_EP2OUT_STOP		0x53	//
#define	CMD_PORT_CFG		0x54	//addr_mask, out_pins
#define	CMD_REG_READ		0x55	//addr	(return 1byte)
#define	CMD_REG_WRITE		0x56	//addr, value
#define	CMD_PORT_READ		0x57	//(return 1byte)
#define	CMD_PORT_WRITE		0x58	//value
#define	CMD_IFCONFIG		0x59	//value
#define	CMD_MODE_IDLE		0x5a
#define CMD_EP4IN_START		0x5b	//
#define	CMD_EP4IN_STOP		0x5c	//
#define	CMD_IR_CODE			0x5d	//val_l, val_h (0x0000:non 0xffff:BUF output)
#define CMD_IR_WBUF			0x5e	//ofs, len, data, ....
#define	CMD_IR_RBUF			0x5f	//ofs (return 64byte)
#define CMD_TSBCAS_INIT		0x70	// TS - BCAS シンクロスタート
#define CMD_TSBCAS_START	0x71	// TS - BCAS シンクロスタート
#define CMD_TSBCAS_END		0x72	// TS - BCAS 終了
#define CMD_TSBCAS_DEBUGEND	0x73	// TS - BCAS デバッグ終了
#define CMD_TSBCAS_MONREG	0x74
#define CMD_TSBCAS_REGR		0x75
#define CMD_TSBCAS_REGW		0x76
#define CMD_TSBCAS_WEP4BCL	0x77

//#define _DEBUG

void TSBCAS_End(void)
{
	start_tsbcas = 0;

	IOD = MODE_IDLE | (IOD & 0x3f);		// Mode:IDLE

	EP6FIFOCFG = 0x04;	// EP6IN STOP
	EP4FIFOCFG = 0x04;	// EP4IN STOP

	FIFORESET = 0x04;	// reset, FIFO 4
	FIFORESET = 0x06;	// reset, FIFO 6

#ifdef _DEBUG
	XAUTODAT2=0xF4;ret_cnt++;		
	XAUTODAT2=0x00;ret_cnt++;		
#endif

}

void TSBCAS_Init(void)
{
	start_ts = 0;
	before_ep4bc = 0xff;
	time_out = 0;
	int_flg = 0;
	bcas_time_out = 0;
	
	IFCONFIG = 0xE3; SYNCDELAY;		//slave FIFO, IFCLK=48MHz, IFCLK出力,  同期(Sync)モード

	EP6FIFOCFG = 0x04; SYNCDELAY;	// EP6IN STOP
	EP4FIFOCFG = 0x08; SYNCDELAY;	// EP4IN STOP

	EP4AUTOINLENH = 0x00; SYNCDELAY;
	EP4AUTOINLENL = 0x45; SYNCDELAY;

	EP4FIFOPFH =  0xc0; SYNCDELAY;	// DECIS=1	PKTSTAT=1
	EP4FIFOPFL = 0x30; SYNCDELAY;	// notify over 0x30 bytes

	FIFORESET = 0x04; SYNCDELAY;	// reset, FIFO 4
	
	IOD = MODE_START | (IOD & 0x3f);	// EP4 Start!!!

#ifdef _DEBUG
	XAUTODAT2=0xF0;ret_cnt++;		
	XAUTODAT2=0x00;ret_cnt++;		
#endif

}

void TSBCAS_Start(void)
{
	FIFORESET = 0x04; SYNCDELAY;	// reset, FIFO 4

	FIFORESET = 0x06;	// reset, FIFO 6
	SYNCDELAY;

	IOD = MODE_START | (IOD & 0x3f);	// EP4 Start!!!

	start_tsbcas = 1;

#ifdef _DEBUG
	XAUTODAT2=0xF0;ret_cnt++;		
	XAUTODAT2=0x01;ret_cnt++;		
#endif

}

void TS_Start(void)
{
	FIFORESET = 0x06;	// reset, FIFO 6
	SYNCDELAY;

	EP6FIFOCFG = 0x0C;	//8bit, Auto-IN
	SYNCDELAY;
								// EP6 Start!!
	start_ts = 1;
}

void BCAS_Poll(void)
{

	poll_cnt++;

	if(int_flg){
		XAUTODAT2=0xE0;ret_cnt++;				
		XAUTODAT2=int_flg;ret_cnt++;			
		int_flg = 0;
	}

	if( !( EP24FIFOFLGS & 0x20 ) ) { // EP4EF=0 when FIFO “not” empty, host sent pkt.

	
#ifdef _DEBUG
		XAUTODAT2=0xF2;ret_cnt++;				
		XAUTODAT2=EP24FIFOFLGS;ret_cnt++;		
#endif
		
		if(time_out++ > 0xa00){
#ifdef _DEBUG
		XAUTODAT2=0xE2;ret_cnt++;				
#endif
			INPKTEND = 0x04; 						// firmware commits EP4 packet
			SYNCDELAY;
			time_out = 0;
		}
		
#ifdef _DEBUG
		XAUTODAT2=EP24FIFOFLGS;ret_cnt++;		
#endif

		if(start_ts == 0 &&
			EP4FIFOBUF[3] == 0x90 &&
			EP4FIFOBUF[4] == 0x34 
		){

#ifdef _DEBUG
			XAUTODAT2=0xF3;ret_cnt++;		
			XAUTODAT2=0x00;ret_cnt++;		
#endif
			TS_Start();
		}

	} else {
		time_out = 0;
		bcas_time_out++;
		if(bcas_time_out > 0xa00 && start_ts == 0){
			TS_Start();
		}
	}
}


void TD_Poll(void)              // Called repeatedly while the device is idle
{
	u8 i, j;
	u8 cmd_cnt;
	u8 addr_mask;
//	u16 adr;


	ret_cnt=0;

	if(start_tsbcas){
#ifdef _DEBUG
		AUTOPTRH2=MSB( &EP1INBUF );
        AUTOPTRL2=LSB( &EP1INBUF );
#endif
		BCAS_Poll();
	}

	if(!(EP1OUTCS & bmEPBUSY))
	{
		
		cmd_cnt=EP1OUTBC;
		AUTOPTR1H=MSB( &EP1OUTBUF );
        AUTOPTR1L=LSB( &EP1OUTBUF );

#ifdef _DEBUG
		if(ret_cnt==0){
			AUTOPTRH2=MSB( &EP1INBUF );
	        AUTOPTRL2=LSB( &EP1INBUF );
	    }
#else
		AUTOPTRH2=MSB( &EP1INBUF );
        AUTOPTRL2=LSB( &EP1INBUF );
#endif

		for(;;){
			if(cmd_cnt-- == 0) break;
			switch(XAUTODAT1){
			case CMD_IR_WBUF:
				i = XAUTODAT1;
				j = XAUTODAT1;
				cmd_cnt -= 2+j;
				for(;;){
					ir_wbuf[i++] = XAUTODAT1;
					if(--j == 0) break;
				}
				ir_wbuf_len = i;
				ir_wbuf_idx = 0;
				break;
			case CMD_IR_RBUF:
#if 0
				if(XAUTODAT1 == 0)
					ir_rbuf_idx_cpy = ir_rbuf_idx;
				cmd_cnt--;
				for(i=0; i<64; i++){
					XAUTODAT2 = ir_rbuf[--ir_rbuf_idx_cpy];
					ret_cnt++;
				}
#endif
				break;
			case CMD_IR_CODE:
				*((u8 *)&ir_code+1) = XAUTODAT1;
				*((u8 *)&ir_code) = XAUTODAT1;
				cmd_cnt-=2;
				break;
			case CMD_REG_WRITE:
#if 0			// Shrink
				IOD = MODE_REGW | (IOD & addr_mask) | XAUTODAT1;
				IFCONFIG = 0xE0;	//48MHz IFCLK & PORTB enable
				OEB = 0xff;			//PORTB all output
				IOB = XAUTODAT1;
				cmd_cnt-=2;
#endif
				break;
			case CMD_REG_READ:
#if 0			// Shrink
				IOD = MODE_REGR | (IOD & addr_mask) | XAUTODAT1;
				IFCONFIG = 0xE0;	//48MHz IFCLK & PORTB enable
				OEB = 0x00;			//PORTB all input
				XAUTODAT2=IOB;
				ret_cnt++;
				cmd_cnt-=1;
#endif
				break;
			case CMD_PORT_WRITE:
				IOD = (IOD & ~addr_mask) | XAUTODAT1;
				cmd_cnt-=1;
				break;
			case CMD_PORT_READ:
				XAUTODAT2=IOD;
				ret_cnt++;
				break;
			case CMD_PORT_CFG:
				addr_mask = (XAUTODAT1 | 0xc0);
				OED = XAUTODAT1 | addr_mask;
				addr_mask = ~addr_mask;
 			    cmd_cnt-=2;
				break;
			case CMD_IFCONFIG:
				val_ifconfig = XAUTODAT1;
				cmd_cnt-=1;
				break;
			case CMD_EP6IN_START:
/*				IFCONFIG = val_ifconfig;

				FIFORESET = 0x06;	// reset, FIFO 6
				SYNCDELAY;

				EP6FIFOCFG = 0x0C;	//8bit, Auto-IN
				SYNCDELAY;

				IOD = MODE_START | (IOD & 0x3f);*/

				TS_Start();

				break;
			case CMD_EP6IN_STOP:
				EP6FIFOCFG = 0x04;	//8bit
				break;
			case CMD_EP4IN_START:
#if 0
				IFCONFIG = val_ifconfig;

				FIFORESET = 0x04;	// reset, FIFO 4
				SYNCDELAY;

				EP4FIFOCFG = 0x0C;	//8bit, Auto-IN
				SYNCDELAY;

				IOD = MODE_START | (IOD & 0x3f);
#endif
				break;
			case CMD_EP4IN_STOP:
				EP4FIFOCFG = 0x04;	//8bit
				break;
			case CMD_EP2OUT_START:
#if 0			// Shrink
				IFCONFIG = val_ifconfig;

				FIFORESET = 0x02;	// reset, FIFO 2
				SYNCDELAY;

				OUTPKTEND = 0x82;
				SYNCDELAY;
				OUTPKTEND = 0x82;
				SYNCDELAY;
				OUTPKTEND = 0x82;
				SYNCDELAY;
				OUTPKTEND = 0x82;
				SYNCDELAY;
				EP2FIFOCFG = 0x10;	//8bit, Auto-OUT
				SYNCDELAY;

				IOD = MODE_START | (IOD & 0x3f);
#endif
				break;
			case CMD_EP2OUT_STOP:
				EP2FIFOCFG = 0x04;	//8bit
				break;
			case CMD_MODE_IDLE:
				IOD = MODE_IDLE | (IOD & 0x3f);
				break;

			case CMD_TSBCAS_INIT:
				TSBCAS_Init();
				break;

			case CMD_TSBCAS_START:
				TSBCAS_Start();
				break;
				
			case CMD_TSBCAS_END:
				EP4BCL = 0x04; 						// firmware commits EP4 packet
				TSBCAS_End();
				break;

#ifdef _DEBUG
			case CMD_TSBCAS_DEBUGEND:
				XAUTODAT2 = 0xff;
				ret_cnt++;				
				break;

			case CMD_TSBCAS_MONREG:
				XAUTODAT2=0xD0;		ret_cnt++;			
				XAUTODAT2=EP4BCH;	ret_cnt++;
				XAUTODAT2=EP4BCL;	ret_cnt++;
				XAUTODAT2=EP24FIFOFLGS;ret_cnt++;		
				XAUTODAT2=EP4FIFOCFG;ret_cnt++;		
				XAUTODAT2=EP4CS;	ret_cnt++;		
				XAUTODAT2=EP4FIFOIE;ret_cnt++;		
				XAUTODAT2=0x00;		ret_cnt++;
				XAUTODAT2=int_flg;	ret_cnt++;
				XAUTODAT2=start_ts;	ret_cnt++;
				XAUTODAT2=start_tsbcas;	ret_cnt++;
				XAUTODAT2=poll_cnt;	ret_cnt++;
				XAUTODAT2=before_ep4bc;	ret_cnt++;
				break;

			case CMD_TSBCAS_WEP4BCL:
				EP4AUTOINLENH = XAUTODAT1;
				cmd_cnt --;
				EP4AUTOINLENL = XAUTODAT1;
				cmd_cnt --;
				break;

#if 0
			case CMD_TSBCAS_REGW:
				adr = XAUTODAT1;
				cmd_cnt-=1;
				adr |= XAUTODAT1<<8;
				cmd_cnt-=1;
				*((u8*)adr) = XAUTODAT1;
				cmd_cnt-=1;
				break;

			case CMD_TSBCAS_REGR:
				adr = XAUTODAT1;
				cmd_cnt-=1;
				adr |= XAUTODAT1<<8;
				cmd_cnt-=1;
				XAUTODAT2 = adr >> 8;
				ret_cnt++;
				XAUTODAT2 = adr & 0xff;
				ret_cnt++;

				XAUTODAT2 = EP24FIFOFLGS;
				ret_cnt++;

				XAUTODAT2 = *((u8*)0x00ab);
				ret_cnt++;
								
				XAUTODAT2 = *((u8*)adr);
				ret_cnt++;
				break;
#endif
#endif
			}
		}
		EP1OUTBC=0;	//arm EP1OUT
		if(ret_cnt)
		{
			EP1INBC=ret_cnt;
			ret_cnt=0;
		}
	}

#ifdef _DEBUG
	if(ret_cnt){
		EP1INBC=ret_cnt;
	}
#endif

}

BOOL TD_Suspend(void)          // Called before the device goes into suspend mode
{
   return(TRUE);
}

BOOL TD_Resume(void)          // Called after the device resumes
{
   return(TRUE);
}

//-----------------------------------------------------------------------------
// Device Request hooks
//   The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------

BOOL DR_GetDescriptor(void)
{
   return(TRUE);
}

BOOL DR_SetConfiguration(void)   // Called when a Set Configuration command is received
{
   Configuration = SETUPDAT[2];
   return(TRUE);            // Handled by user code
}

BOOL DR_GetConfiguration(void)   // Called when a Get Configuration command is received
{
   EP0BUF[0] = Configuration;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);            // Handled by user code
}

BOOL DR_SetInterface(void)       // Called when a Set Interface command is received
{
   AlternateSetting = SETUPDAT[2];
   return(TRUE);            // Handled by user code
}

BOOL DR_GetInterface(void)       // Called when a Set Interface command is received
{
   EP0BUF[0] = AlternateSetting;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);            // Handled by user code
}

BOOL DR_GetStatus(void)
{
   return(TRUE);
}

BOOL DR_ClearFeature(void)
{
   return(TRUE);
}

BOOL DR_SetFeature(void)
{
   return(TRUE);
}

BOOL DR_VendorCmnd(void)
{
  BYTE tmp;
  
  switch (SETUPDAT[1])
  {
     case VR_NAKALL_ON:
        tmp = FIFORESET;
        tmp |= bmNAKALL;      
        SYNCDELAY;                    
        FIFORESET = tmp;
        break;
     case VR_NAKALL_OFF:
        tmp = FIFORESET;
        tmp &= ~bmNAKALL;      
        SYNCDELAY;                    
        FIFORESET = tmp;
        break;
     default:
        return(TRUE);
  }

  return(FALSE);
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
   GotSUD = TRUE;            // Set flag
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUDAV;         // Clear SUDAV IRQ
}

// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUTOK;         // Clear SUTOK IRQ
}

void ISR_Sof(void) interrupt 0
{
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSOF;            // Clear SOF IRQ
}

void ISR_Ures(void) interrupt 0
{
   // whenever we get a USB reset, we should revert to full speed mode
   pConfigDscr = pFullSpeedConfigDscr;
   ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
   pOtherConfigDscr = pHighSpeedConfigDscr;
   ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;

   EZUSB_IRQ_CLEAR();
   USBIRQ = bmURES;         // Clear URES IRQ
}

void ISR_Susp(void) interrupt 0
{
   Sleep = TRUE;
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUSP;
}

void ISR_Highspeed(void) interrupt 0
{
   if (EZUSB_HIGHSPEED())
   {
      pConfigDscr = pHighSpeedConfigDscr;
      ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
      pOtherConfigDscr = pFullSpeedConfigDscr;
      ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
   }

   EZUSB_IRQ_CLEAR();
   USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
void ISR_Ep2inout(void) interrupt 0
{
}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
	int_flg |= 0x04;
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
	int_flg |= 0x01;
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}
